1. Field of the Invention
The present invention relates generally to Complementary Metal-Oxide-Semiconductor Random Access Memories (CMOS RAMs), and more particularly to using a balanced number of N-MOS and P-MOS transistors in a RAM cell to save layout area.
2. Description of the Background Art
CMOS RAM cells comprise N-MOS and P-MOS type transistors, each type of which requires layout areas separate from the other type.
FIG. 1 shows a prior art two-port RAM cell 100 that includes two P-MOS transistors P126 and P134 and eight N-MOS transistors N106, N130, N138, N108, N 110, N114, N118, and N122. Transistors P126 and N130 form an inverter I102 while transistors P134 and N138 form an inverter I104. The two inverters I102 and I104 are "cross-coupled," that is, the output of inverter I102 is connected to the input of inverter I104 and the output of inverter I104 is connected to the input of inverter I102.
Lines BL1, BL2, BL1N, and BL2N are referred to as "bit lines."
Line WL1, together with transistors N106, N130, N138, and N108, is referred to as a read-write port since line WL1 enables both reading from and writing to RAM cell 100. Line WL2, together with transistors N110, N114, N118, and N122, is referred to as a read-port because line WL2 enables only reading from RAM cell 100. Lines WL1 and WL2 are also referred to as "word lines."
RAM cell 100 has significantly fewer P-MOS transistors than N-MOS transistors, i.e., two P-MOS transistors P126 and P134 versus eight N-MOS transistors N106, N130, N138, N108, N110, N114, N118, and N122. As the number of ports in RAM cell 100 increases, the unbalance between the number of P-MOS and N-MOS transistors increases.
FIG. 2 shows a prior art three-port RAM cell 200, which is equivalent to RAM cell 100 with a second read-port WL3 constituted by the four N-MOS transistors N142, N146, N150, and N154. RAM cell 200 thus has two P-MOS transistors P126 and P134 and 12 N-MOS transistors N106, N130, N138, N108, N110, N114, N118, N122, N142, N146, N150, and N154. The ratio of P-MOS transistors to N-MOS transistors of 1/4 in cell 100 decreases to 1/6 in cell 200. Because the ports are constituted by N-MOS transistors, this ratio continues to decrease as the number of ports increases. Consequently, since the layout areas for a P-MOS transistor and for an N-MOS transistor must be separated by at least the minimum distance specified by the layout design rules, the unbalanced number of P-MOS and N-MOS transistors wastes layout area.
FIGS. 3A and 3B show two prior art layouts 300A and 300B for either RAM cell 100 or 200. Layouts 300A and 300B each include areas P304 for P-MOS transistors, areas N308 for N-MOS transistors, and unused areas U312. The suffixes A and B correspond to layouts 300A and 300B, respectively. Unused areas U312 are wasted and should be minimized. Even though layout 300B is preferable to layout 300A because the unused area U312B is smaller than the unused area U312A, both unused areas U312A and U312B increase the total layout area. Possibilities for reducing unused areas U312 while providing the same RAM cell circuit are limited because layout design rules require a minimum spacing between area P304 and area N308 to separate P-MOS transistors from N-MOS transistors. The typical spacing requirement is 2.4 .mu.m for 0.35 .mu.m technology where 0.35 .mu.m denotes the minimum manufacturable transistor gate length of the technology.
What is needed, therefore, is a method for improving the deficient layout schemes of the prior art, while maintaining circuit functionalities.